FIG. 1 (Prior Art) is a simplified diagram of two logic modules 1 and 2 of a field programmable gate array (FPGA). An FPGA typically has numerous logic modules. Logic modules may be arranged in a two dimensional matrix having rows and columns with I/O modules surrounding the matrix at the periphery of the integrated circuit chip.
To realize a circuit desired by the user, selected logic in selected logic modules is connected to selected logic in other selected logic modules by programming the appropriate antifuses of a programmable interconnect structure. In FIG. 1, a portion of the programmable interconnect structure having horizontally extending routing conductors, vertically extending routing conductors, and antifuses is illustrated. Antifuses are illustrated with the symbol "X". Logic modules have net drivers 3-6 for driving logic signals out of the logic modules and onto the routing conductors of the interconnect structure. If, for example, it were desired to couple the output of net driver 3 of logic module 1 to the input 7 of logic module 2, then antifuses 8 and 9 would be programmed to couple horizontal routing conductor 10 to vertical routing conductor 11 and to couple vertical routing conductor 11 to horizontal routing conductor 12.
To program antifuse 8, for example, vertical routing conductor 11 may be coupled to ground potential (for example, 0 volts) and a programming voltage (for example, 12 volts) may be placed on horizontal routing conductor 10 such that a programming current flows through antifuse 8 to program antifuse 8 to form a permanent low impedance connection. For additional background information on field programmable gate arrays, logic modules, and antifuses, see: U.S. Pat. No. 5,416,367, U.S. Pat. No. 5,424,655, U.S. Pat. No. 5,196,724, U.S. Pat. No. 5,557,136, and U.S. Pat. No. 5,544,070 (the subject matter of these patents is incorporated herein by reference). To prevent high voltages from damaging the low voltage logic transistors of the net drivers 3-6 during antifuse programming, the net drivers of the logic modules are provided with protection transistors. During antifuse programming, these protection transistors are made nonconductive.
FIG. 2 (Prior Art) is a more detailed diagram of net driver 3. Net driver 3 involves a P-channel low voltage logic transistor 13, an N-channel low voltage logic transistor 14, a relatively large high voltage N-channel protection transistor 15 and a relatively small high voltage N-channel protection transistor 16. Transistors 13 and 14 form an inverter.
During normal operation of the circuit programmed into the FPGA, the output of the inverter is coupled to horizontal routing conductor 10 because protection transistors 15 and 16 are conductive due to the gate of protection transistor 15 being coupled to V.sub.CC (for example, 5.0 volts) and the gate of protection transistor 16 being coupled to a charge pump voltage V.sub.CP (for example, 7.8 volts). During antifuse programming, to isolate the output of the inverter from high voltages that could be present on horizontal routing conductor 10, protection transistors 15 and 16 are made nonconductive by coupling the gates of protection transistors 15 and 16 to ground potential (for example, 0 volts).
To achieve high operating speed of the user's circuit programmed into the FPGA, it is desired that net driver 3 be able to switch the digital logic level at input 7 as fast as possible. Due to the capacitive load of the routing conductors and programmed antifuses downstream of the programmed antifuses 8 and 9 and the capacitive load of input 7, it may be believed that the net driver should be fashioned to supply as large a current as possible during switching. When certain types of antifuses are used, however, this is not the case.
In some antifuse architectures, the electrical characteristics of a programmed antifuse may be altered if the peak operating current flowing through the antifuses during normal circuit operation exceeds a maximum permissible operating current. In certain amorphous silicon antifuses, for example, this value may be approximately 70 percent of the maximum DC programming current with which the antifuse was programmed. It is undesirable that the electrical characteristics of antifuses change during normal operation of the circuit programmed into the FPGA. Accordingly, there may be an upper limit on the peak operating current that can pass through a programmed antifuse in a net during switching and this maximum permissible operating current may depend on the programming current used to program the antifuse. The switching current sinking and sourcing capability of the net drivers 3-6 is therefore set close to this maximum permissible operating current to achieve the highest switching speeds possible with reliable operation.
FIG. 3 (Prior Art) is a graph illustrative of the drain-to-source current IDS of a field effect transistor versus drain-to-source voltage V.sub.DS for two gate-to-source voltages (V.sub.GS =3.3 volts and V.sub.GS =5.0 volts). As the gate-to-source voltage decreases, the drain-to-source current decreases. Accordingly, reducing the supply voltage V.sub.CC to the field programmable gate array of FIGS. 1 and 2 would result in the net drivers 3-6 being able to sink and source less switching current during normal circuit operation. If the switching current capabilities of the net drivers 3-6 were set for a 5.0 volt V.sub.CC operation, then it is likely that the switching current capabilities of net drivers 3-6 would be less than desired for 3.3 volt V.sub.CC operation assuming that the antifuses are programmed with the same programming current.
A reliable antifuse field programmable gate array is desired that can operate at high switching speeds at both at a high supply voltage (for example, V.sub.CC =5.0 volts) as well as at a lower supply voltage (for example, V.sub.CC =3.3 volts)